Modern microprocessor built from complementary carbon nanotube transistors (2024)

Extended Data Fig. 1 Fabrication process flow for RV16X-NANO.

The fabrication process is a 5-metal-layer (M1 to M5) process and involves >100 individual process steps. s-CNT, semiconducting CNT; S/D, source/drain.

Extended Data Fig. 2 Microscopy image of a full fabricated RV16X-NANO die.

The processor core is in the middle of the die, with test circuitry surrounding the perimeter (when the RV16X-NANO is diced for packaging, these test structures are removed). The test structures include test structures for monitoring fabrication, as well as for measuring and characterizing all of the 63 standard cells in our standard cell library.

Extended Data Fig. 3 CNFET standard cell library.

List of all of the standard cells comprising our standard cell library, along with a microscopy image of each fabricated standard cell, the schematic of each cell, and a typical measured waveform from each fabricated cell. As expected for static CMOS logic stages, the CNFET logic stages exhibit output voltage swing exceeding 99% of V_DD, and achieve gain of >15. Experimental waveforms are not shown for cells whose functionality is not demonstrated by output voltage as a function of either input voltage or time; for example, for cells without outputs (for example, fill cells: cell names that start with ‘fill_’ or decap cells:cell names that start with ‘decap_’), for cells whose output is constant (tied high/low: cell names that start with ‘tie_’), or for transmission gates (cell names that start with ‘tg_’).

Extended Data Fig. 4 Image of a completed RV16X-NANO 150-mm wafer.

Each wafer includes 32 dies (single die shown in Extended Data Fig. 2).

Extended Data Fig. 5 Negligible effect of RINSE on CNTs and CNFETs.

a, CNT density is the same pre- versus post-RINSE. b, CNFET I_D–V_GS exhibit minimal change for sets of CNFETs fabricated with and without RINSE (V_DS = −1.8 V for all measurements shown). Both samples came from the same wafer, which was diced after the CNT deposition but before the RINSE process. One sample underwent RINSE while the other sample did not. c, CNFETs can still be doped NMOS after the RINSE process, leveraging our MIXED process (V_DS = −1.2 V for all measurements shown).

Extended Data Fig. 6 MIXED CNFET CMOS characterization.

a, Definitions ofkey metrics for characterizing logic gates, including SNM, gain and swing. V_OH, V_IH, V_IL and V_IL (labelled on the VTCsin a, where (V_IL, V_OH) and (V_IH, V_OL) are the points on the VTC whereΔV_OUT/ΔV_IN = −1) are used to extract the noise margin: SNM=min(SNM_H, SNM_L). b, Key metrics extracted for the 10,400 CNFET CMOS nor2 logic gates measured in Fig. 5 (metrics defined in a). This is the largest CNT CMOS demonstration to date, to our knowledge. V_DD is 1.2V. c, SNM is extracted based on the distributions from b. We analyse >100 million logic gate pairs based on these experimental results. d, Spatial dependence of V_IH (as an example parameter to compute SNM). Each pixel represents the V_IH of the nor2 at that location in the die. Importantly, V_IH increases across the die (from top to bottom). The change in V_IH corresponds with slight changes in CNFET threshold voltage. The fact that the threshold voltage variations are not independently and identically distributed (i.i.d.), but rather have spatial dependence, illustrates that a portion of the threshold voltage variations (and therefore variation in SNM) is due to wafer-level processing-related variations (CNT deposition is more uniform across the 150-mm wafer). Future work should optimize processing steps, for example, increasing the uniformity of the atomic-layer-deposition oxide deposition used for electrostatic doping to further improve SNM for realizing VLSI circuits. e, Wafer-scale CNFET CMOS characterization. Measurements from 4 dies across 150-mm wafer (1,000 CNFET CMOS nor2 logic gates are sampled randomly from the 10,400 such logic gates in each die). No outliers are excluded. Yield and performance variations are negligible across thewafer, illustrated by the distribution of the output voltage swing.

Extended Data Fig. 7 Effect of metallic CNTs on digital VLSI circuits.

a, Reduction in CNFET EDP benefits versus p_S (metallic CNTs increase I_OFF, degrading EDP). p_S ≈ 99.999%, sufficient to minimize EDP cost due to metallic CNTs to ≤5%. b, p_NMS versus p_S (metallic CNTs degrade SNM), (shown for SNM_R=V_DD/5, and for a circuit of one million logic gates). Although 99.999% p_S is sufficient to limit EDP degradation to ≤5%, panel b shows that SNM imposes far stricter requirements on purity: p_S ≈ 99.999999% (that is, number of 9s is 8) to achieve p_NMS≥99% (number of 9s is 2). Results in panels a and b are simulated for VLSI circuit modules from a 7-nm node processor core (seeSupplementary Information and Methods for additional details).

Extended Data Fig. 8 Methodology to solve VTCs using CNFET I–V measurements.

a, Experimentally measured I_D versus V_GS for all 1,000 NMOS (V_DS=1.8 V) and 1,000 PMOS CNFETs (V_DS=−1.8V), with no CNFETs omitted. Metallic CNTs (m-CNTs) present in some CNFETs result in high off-state leakage current (I_OFF=I_D at V_GS=0V). b, VTC and SNM parameter definitions, for example, for (nand2, nor2). DR is the driving logic stage; LD is the loading logic stage. SNM=min(SNM_H, SNM_L), where SNM_H=V_OH^(DR) – V_IH^(LD) and SNM_L=V_IL^(LD) – V_OL^(DR). c–e, Methodology to solve VTCs (for example, for nand2) using experimentally measured CNFET I–V curves. c, Example I_D versus V_DS for NMOS and PMOS CNFETs (V_GS is swept from −1.8 V to 1.8 V in 0.1-V increments). d, Schematic. To solve a VTC (for example, V_OUT versus V_A with V_B=V_DD): for each V_A, find V₁ and V_OUT such that i_PA + i_PB=i_NA=i_NB (DC, direct current, convergence). e, Current in the pull-up network (i_PU, where i_PU=i_PA + i_PB, and i_PA and i_PB are the labelled drain currents of the PMOS FETs gated by A and B, respectively) and current in thepull-down network (i_PD, where i_PD=i_NA=i_NB, and i_NA and i_NB are the labelled drain currents of the NMOS FETs gated by A and B, respectively) versus V_OUT and V_A. The VTC is seen where these currents intersect. CNFETs are fabricated at a ~1 µm technology node, and theCNFET width is 19 µmin panela.

Extended Data Fig. 9 DREAM implementation and methodology.

a, Standard cell layouts (derived using the ‘asap7sc7p5t’standard cell library³⁷), illustrating the importance of CNT correlation: because the length of CNTs (which can be ofthe order of hundreds of micrometres) is typically much longer compared withthe CNFET contacted gate pitch (CGP, for example about42–54 nm for a 7-nm node³⁷), the number of s-CNTs and m-CNTs in CNFETs can be uncorrelated or highly correlated depending on the relative physical placement of CNFET active regions³⁸. For many CMOS standard cell libraries at sub-10-nm nodes (for example refs^37,39), the active regions of FETs are highly aligned, resulting in highly correlated number of m-CNTs among CNFETs in library cells, further degrading VTCs (becauseone m-CNT can affect multiple CNFETs simultaneously). b–f, Generating a variation-aware CNFET SNM model, shown for a D-flip-flop (dff) derived from the asap7sc7p5t standard cell library³⁷. b, Layout used to extract netlists for each logic stage. c, Schematic: CNFETs are grouped by logic stage (with nodes arbitrarily labelled ‘D’, ‘MH’, ‘MS’, ‘SH’, ‘SS’, ‘CLK’, ‘clkn’, ‘clkb’and ‘QN’ for ease of reference). d, For each extracted netlist, there can be multiple VTCs: for each logic stage output, a logic stage input is sensitized if the output state (0 or 1) depends on the state of that input (given the states of all the other inputs). For example, for a logic stage with Boolean function: Y = !(A*B+C), C is sensitized when (A, B) = (0, 0), (0, 1)or (1, 0). We simulate all possible VTCs (over all logic stage outputs and sensitized inputs), and also in the presence of m-CNTs. For example, panel dshows a subset of the VTCs for the logic stage in panel bwith output node ‘MH’(labelled in panelc), and sensitized input ‘D’(with labelled nodes (‘clkb’, ‘clkn’, ‘MS’) = (0, 1, 0)). The dashed line indicates VTC with no m-CNTs, and the solid lines are example VTCs in the presence of m-CNTs (including the effect of CNT correlation). In each case, we model V_OH, V_IH, V_ILand V_OL as affine functions of the number of m-CNTs (M_i) in each of r regions (M₁, ..., M_r), with calibration parameters in the static noise margin (SNM) model matrix T (shown in panel f). e,Example calibration of the SNM model matrix T for the VTC parameters extracted in panel d; thesymbols are VTC parameters extracted from circuit simulations (using Cadence Spectre),andsolid lines are the calibrated model. f,Affine model form. g–j, VLSI design and analysis methodology. g, Industry-practice physical design flow to optimize energy and delay of CNFET digital VLSI circuits, including: (1) library power/timing characterization (using Cadence Liberate) across multiple V_DDand using parasitics extracted from standard cell layouts (derived from the asap7sc7p5t standard cell library), in conjunction with a CNFET compact model⁸. (2) Synthesis (using Cadence Genus), place-and-route (using Cadence Innovus) with back-end-of-line (BEOL) wire parasitics from the ASAP7 process design kit (PDK). (3) Circuit EDP optimization: we sweep both V_DD and target clock frequency (during synthesis/place-and-route) to create multiple physical designs. The one with best EDP is used to compare design options (for example, DREAM versus baseline). h, Subset of logic gates in an example circuit module, showing the effect of CNT correlation at the circuit level (for example, the m-CNT counts of CNFETs P3,1 and P5,1 are both equal to M₁ + M₂ + M₃)⁴⁰. i, Distribution of SNM over all connected logic stage pairs, for a single sample of the circuit m-CNT counts. The minimum SNM for each trial limits the probability that all noise margin constraints in the circuit are satisfied (p_NMS). j,Cumulative distribution of minimum SNM over 10,000 Monte Carlo trials, shown for multiple target p_S values, where p_S is the probability that a given CNT is a semiconducting CNT. These results are used to find p_NMSversusp_S for a target SNM requirement (SNM_R), where p_NMS is the fraction of trials that meet the SNM requirement for all logic stage pairs. We note that p_NMS can then be exponentiated to adjust for various circuit sizes based on the number of logic gates. k, CNFET compact model parameters (forexample, 7-nm node).

Supplementary Information

Supplementary Text, Data, Tables and References.

Cite this article

Hills, G., Lau, C., Wright, A. et al. Modern microprocessor built from complementary carbon nanotube transistors. Nature 572, 595–602 (2019). https://doi.org/10.1038/s41586-019-1493-8

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• Received: 16 January 2019

• Accepted: 03 July 2019

• Published: 28 August 2019

• Issue Date: 29 August 2019

• DOI: https://doi.org/10.1038/s41586-019-1493-8